The present invention relates generally to an integrated circuit (IC) design, and more particularly to a method for providing a multiple-port static-random-access-memory (SRAM) cell structure with balanced read and write operation speeds and an improved noise margin.
SRAM devices have become increasingly popular as data storage units for high-speed communication devices, image processing devices, and other system-on-chip (SOC) products. A SRAM device is typically comprised of a logic circuit portion and a memory cell portion, which includes a plurality of cells arranged in one or more arrays. The SRAM cells, based on their structures, can be categorized as single-port cells, two-port cells, dual-port cells, and multiple-port cells. SRAM devices made of two-port, dual-port or multiple-port cells have become increasingly popular, as they are particularly suitable for parallel operations.
FIG. 1A schematically illustrates a conventional two-port SRAM cell 100 that is implemented with eight transistors. The conventional two-port SRAM cell 100 includes two PMOS transistors 102 and 104 and six NMOS transistors 106, 108, 110, 112, 114, and 116. The PMOS transistors 102 and 104 function as pull-up devices, while the NMOS transistors 106 and 108 function as pull-down devices. The NMOS transistors 110 and 112 function as pass-gate devices for read or write operations. The sources of the PMOS transistors 102 and 104 are both connected to a supply voltage Vcc, while the sources of the NMOS transistors 106 and 108 are both connected to a complementary supply voltage, such as ground or Vss. The gates of the PMOS transistor 102 and NMOS transistor 106 are coupled at a node 118, while their drains are also tied together at a node 120. The PMOS transistor 104 and the NMOS transistor 108 also having gates coupled together at the node 120, and drains at the node 118. The node 118 is coupled to a complementary read/write port bit line BLB via the NMOS transistor 112, which is controlled by a read/write word line WL. The node 120 is coupled to a read/write port bit line BL via the NMOS transistor 110, which is also controlled by the same read/write word line WL. In some special cases, this read/write port may serve only as a write port without the read function.
The read port portion of the conventional two-port SRAM cell 100 includes the NMOS transistor 114, which acts as a pull-down device and the NMOS transistor 116, which acts as a pass-gate device. A gate of the NMOS transistor 114 is connected to the node 120 (or 118), while its source is tied to the complementary supply voltage, such as ground or Vss. A high signal at the node 120 (or 118) can turn the NMOS transistor 114 on and ground the read port bit line BL when the NMOS transistor 116 is turned on by a high signal on the read word line WL.
FIG. 1B illustrates a layout diagram 122 of the metal routing for the conventional two-port SRAM cell 100 shown in FIG. 1A. The layout diagram 122 shows the metal routing for most of the interconnections used within the conventional two-port SRAM cell 100 of FIG. 1A. These interconnections include several power lines such as a supply voltage Vcc line 124, a complementary supply voltage Vss line 128, a landing pad 126 for another complementary supply voltage Vss line (not shown in this figure), and several bit lines and word lines. The bit lines shown are a read/write port bit line BL 130, a complementary read/write port bit line BLB 132, and a read port bit line BL 134. A read/write word line WL 136 is shown lined up in parallel with a read word line WL 138 on a metallization layer higher than that on which the Vcc line 124, the Vss line 128, the landing pad 126, the read/write port bit line DL 130, the complementary read/write port bit line BLB 132, and read port bit line BL 134 are constructed. Three landing pads 140, 142, and 144 are also implemented in parallel with the bit lines on the same metallization layer. The landing pads 140 and 142 are used for making connections with the read/write word line WL 136, while the landing pad 144 is used for making connections with the read word line WL 138.
One drawback of the conventional two-port SRAM cell 110 is that its layout structure is asymmetric. The read/write port bit line 130 is interposed between the landing pad 140 and the Vcc line 124. However, the complementary read/write port bit line BLB 132 is interposed between the Vss line 128 and the Vcc line 124. This asymmetric layout causes an imbalance of coupling capacitance between the read/write port bit line BL 130 and the complementary read/write port bit line BLB 132. As a result, the SRAM cell 100 suffers from a mismatch between read and write operations, induced by unwanted coupling capacitance and noise.
FIG. 2A schematically illustrates a conventional dual-port SRAM cell 200 that is implemented with eight transistors. The conventional dual-port SRAM cell 200 includes two PMOS transistors 202 and 204 and six NMOS transistors 206, 208, 210, 212, 214, and 216. The dual-port SRAM cell 200 utilizes two sets of bit lines and complementary bit lines for A port (first read/write port) and B port (second read/write port), respectively. The sources of the PMOS transistors 202 and 204 are both connected to a supply voltage Vcc, while the sources of the NMOS transistors 206 and 208 are both connected to a complementary supply voltage, such as ground or Vss. The gates of the PMOS transistor 202 and NMOS transistor 206 are coupled at a node 218. While their drains are also tied together at a node 220. The gates of the PMOS transistor 204 and the NMOS transistor 208 are also coupled together at the node 220, and their drains coupled at the node 218, The node 218 is coupled to an A port (first read/write port) complementary bit line BLB via the NMOS transistor 212 as well as to a B port (second read/write port) complementary bit line BLB via the NMOS transistor 216. The NMOS transistor 212 is controlled by an A port word line, while the NMOS transistor 216 is controlled by a B port word line. The node 220 is coupled to an A port bit line BL via the NMOS transistor 210 as well as to a B port bit line BL via the NMOS transistor 214. The NMOS transistor 210 is controlled by the A port word line while the NMOS transistor 214 is controlled by the B port word line.
FIG. 2B illustrates a layout diagram 222 of the metal routing for the conventional dual-port SRAM cell 200 shown in FIG. 2A. The layout diagram 222 shows interconnections including several supply lines such as a supply voltage Vcc line 224 and two complementary supply voltage Vss lines 226 and 228 as well as several bit lines and word lines. The bit lines shown are an A port bit BL 230, a complementary A port bit line BLB 232, a B port bit line BL 234, and a complementary B port bit line BLB 236. An A port word WL 238 is shown lined up in parallel with a B port word line WL 240. Two landing pads 242 and 244 are also implemented in parallel with the bit lines and supply voltage lines. The landing pad 242 is used for making connections with the A port word line WL 238, while the landing pad 244 is used for making connections with the B port word line WL 240.
Although the conventional dual-port SRAM cell 200 provides a symmetrical layout structure, there is still a balancing issue induced by the coupling capacitance on the bit lines. For example, the placements of the A port bit line BL 230 between the complementary supply voltage Vss line 226 and the landing pad 242, and the placement of the complementary write port bit line BLB 232 between the complementary supply voltage Vss line 226 and the supply voltage Vcc line 224 can create an imbalance of coupling capacitance. The same coupling capacitance imbalance issue may occur for the B port bit line BL 234 and the complementary B port bit line BLB 236, since the B port bit line BL 234 is placed between the complementary supply voltage Vss line 228 and the landing pad 244 and the complementary B port bit line BLB 236 is placed between the complementary supply voltage Vss line 228 and the supply voltage Vcc line 224. An imbalance between the coupling capacitance of the interconnection wires may result in an undesired level of noise margin, thereby hindering the operation speed of the cell.
As such, desirable in the art of integrated circuit designs are new SRAM cell structures with balanced read and write operation speeds and an improved noise margin.